Title image Fall 2019

Lab 1: Digital Logic CAD Tools

The purpose of this lab is to familiarize you with logic gates and basic digital logic design techniques. We will be using a digital logic CAD program, Quartus, to generate our designs using a graphic layout tool. We will then use a second simulation tool, ModelSim, to test our designs and ensure they are working correctly.


  1. Start Quartus by opening a terminal and typing:


    If you want to put quartus in the background, add an ampersand (&) to the end of the command line.

    The first time you open Quartus, it will prompt you for a license. Indicate that you have a license file, then enter /export/opt/altera/12.1/license.dat in the dialog box that appears.

    Quartus should start up and display a window with the option of creating a new project, opening an interactive tutorial, or opening an existing project. It might be a good idea to go through the tutorial on your own time.

    Specify where you want to put the project and a name for it and the top level design entity. As noted, the project name and entity name must be identical. You should put each project in its own sub-directory, probably inside a cs232 folder.

    We have no design files to add, so skip the next screen.

    If you are just simulating, let the device be selected automatically. If you want to use an FPGA board, you will have to set this to the device on the board.

    If you wish, select the device for the DE1 board, which is a Cyclone II FPGA with the name EP2C20F484C7.

    In the EDA Tool settings, set the Simulation entry to ModelSim-Altera with the format VHDL. That should complete your project setup.

    After creating the project, select File::New and pick a Block Diagram/Schematic File.

    In the block diagram file you can now lay out circuits graphically and connect them with virtual wires.

  2. Using the graphic layout tool, make a simple combinational logic tree for the function F = AB + A'B'. Double-click to place a new module. There are many types of modules. We want to use a simple primitive logic gate, as shown below.

    Lay out two 2-input AND gates and one 2-input OR gate to build the circuit. Then connect the output of each AND gate to the inputs on the OR gate. You can click and drag to make wires.

    Create two input pins and one output pin, again by double-clicking and then selecting input or output from the pins category. Place the pins in the upper left (inputs) and upper right (outputs) of your graphical design. Then edit the names so the pins are named A, B, and F.

    Next, make a small wire coming out of each input pin and a small wire coming into the output pin. Label these as A, B, and F, respectively. By labeling wires you can make virtual connections between them.

    Next, add two NOT gates in front of the second AND gate and feed the A and B inputs to the NOT gates. The final circuit is shown below.

    Select File->Save Project and save your work as a bdf file. Since it is the top level file in your project, give it the same name as your project name, in this case circuit1.bdf.

  3. Convert your design to a VHDL file. Select File::Create/Update::Create HDL Design File from Curent File.

    In the popup, select VHDL and click Ok. This should create a vhdl file version of your circuit. The name of the file will end in .vhd

Modeling a Circuit Using GHDL

  1. Select File::Create/Update::Create HDL Design File from Curent File.
  2. In the popup, select VHDL and click Ok. This should create a vhdl file version of your circuit. The name of the file will end in .vhd
  3. Now you need to create a driver file that sends signals into your circuit and accepts the output. An example for the circuit above is testbench.vhd. This file defines three signals: A, B, and F. It then assigns values to A and B at certain time intervals. These values and time intervals form the four possible combinations of A and B. The file then attaches these signals to the circuit you created above. Note that you will need to edit the testbench.vhd file so the component statement label matches the name of the circuit you created. I named mine test, so my version needs to say "component test" in the declaration section and "test port map" in the code section. If your file is named circuit1, then your file needs to say "component circuit1" in the declaration section and "circuit1 port map" in the code section.
  4. Save your VHDL test bench file in the same directory with your circuit's vhdl file.
  5. Run the ghdl tool to compile and simulate your circuit. Remember, I called my circuit circuit1, so my vhdl file is called circuit1.vhd.

    ghdl -a circuit1.vhd testbench.vhd
    ghdl -e testbench
    ghdl -r testbench --vcd=testbench.vcd

  6. Finally, open up the .vcd file in gtkwave.

    gtkwave testbench.vcd

    Once the window opens, select all of your signals and select "Insert". Then click on the "Zoom to Fit" button or set the bounds of the window to 0 ns to 100 ns. You should end up with a visualization like below.

    You can see in this example that the circuit is working properly. The output F is high when A and B are both low (0) or both high (1), and F is low (0) when A and B are not the same value.

Testing a Circuit With the Altera DE1 Board

The Altera DE1 board contains a programmable Field Programmable Gate Array [FPGA]. An FPGA is an electronically configurable set of gates (truth tables) that can be programmed to emulate very complex digital circuits, including CPUs. The Quartus software can compile a digital circuit into a form that can be downloaded onto the FPGA.

The Altera DE1 board contains many different input and output devices, including push-buttons, switches, LEDs, and 7-segment displays. We will be using these input and output devices to control and evaluate our circuits.

You can find the documentation for the DE1 board here. Pages 28-32 specify which output pins control which I/O devices.

In order to program the board, you need to follow these steps.

  1. First, open up the Assignment:Pin Planner window. If you have set up the input and output pins of your circuit correctly, they will show up at the bottom of the window. In the Location column, specify the pin for each input and output. For the simple circuit above, for example, you can use the first two switches (PIN_L21 and PIN_L22) as the inputs and the first red LED (PIN_R20) as the output.

    Once you have specified the pins for all inputs and outputs, close the Pin Planner window and compile your circuit. Any time you change pin assignments, you must recompile.

  2. Second, plug the DE1 board into an available USB port, if it is not already plugged in. If no lights appear, then click the red button to turn on the board. The default program should produce flashing lights.
  3. Third, open up the Tools::Programmer window. If the window says "No Hardware" then click on Hardware Setup, click on the popup menu that says "No Hardware" and select the USB Blaster. Then close the Hardware Setup window.

    At this point, if the Start button is available, click it and it should program the board. If the Start button is not active, then click Select File, navigate to your output_files directory and select the .sof file corresponding to your circuit. If the Start button is now active, click Start and it should program the board. You will know the board has been programmed when the default FPGA program with the flashing lights stops.

    If clicking on the Start button does nothing, please contact me and let me know the (1) name of the machine on which you are working and (2) whether any error messages show up in the Quartus log window.

  4. Once the board is programmed, you can control your circuit by modifying the switches you set up to control the circuit inputs. In the case of the simple circuit above, if the two switches are both 0 or both 1, then the LED should light up.
  5. When you are done with the board, please use the red button to turn it off.

Modeling a Circuit Using ModelSim

If you are using the Web Edition of Quartus on your own laptop, you may be able to use Modelsim to simulate your circuit.

  1. Select Processing::Start::Start EDA_Netlist Writer. Now you are ready to start the simulation process.

    Select Tools::Run Simulation Tool::Gate Level Simulation. This should start ModelSim. If it does not, then you probably need to set the path to ModelSim. Do this by selecting Tool::Options. Then select the panel for EDA simulation tools. It has a line for ModelSim Altera. Enter the string:


    Once ModelSim is open, select Compile::Compile. Then select circui1.vho and click Compile. When the compilation is done, click Done to close the window.

    On the Transcript prompt, type vsim circuit1. This will create two new windows. Go back to the main window and select View::objects. Then detach the objects window, as below, leaving the waveform tab open on the main window.

    In the object window, right-click on object A (one of the input pins) and select Create Wave. We're going to make it a clock input that lasts for 1000ns with a period of 100ns. Make sure you have the units set correctly, as the default may be pico-seconds.

    Finish by specifying the clock to have the proper period (100ns). Repeat the process with object A, but make sure it has a period of 200ns. When you are done, right click in the wave window and select Zoom Full so you can see all of the waveforms.

    Now right-click on the F object and select Add::To Wave::Selected Signals. Finally, in the Transcript window, type run 1000ns. This should simluate the circuit and show you the resulting waveform of the output signal F.

When you have completed the lab assignment, go ahead and get started on the first project.