CS 232: Lab #1

Lab 1: Digital Logic CAD Tools

Main course page

The purpose of this lab is to familiarize you with logic gates and basic digital logic design techniques. We will be using a digital logic CAD program, Quartus, to generate our designs using a graphic layout tool. We will then use a second simulation tool, ModelSim, to test our designs and ensure they are working correctly.

The first two labs you will need to complete on your own. The following labs you may work with a partner.


Tasks

  1. Start Quartus by opening a terminal and typing:

    /opt/altera/11.1sp1/quartus/bin/quartus

    If you want to put quartus in the background, add an ampersand (&) to the end of the command line.

    Quartus should start up and display a window with the option of creating a new project, opening an interactive tutorial, or opening an existing project. It might be a good idea to go through the tutorial on your own time.

    Specify where you want to put the project and a name for it and the top level design entity. As noted, the project name and entity name must be identical. You should put each project in its own sub-directory, probably inside a cs232 folder.

    Specify the device we will eventually program with our circuit. The device on the DE1 board is a Cyclone II FPGA with the name EP2C20F484C7.

    In the EDA Tool settings, set the Simulation entry to ModelSim-Altera with the format VHDL. That should complete your project setup.

    After creating the project, select File::New and pick a Block Diagram/Schematic File.

    In the block diagram file you can now lay out circuits graphically and connect them with virtual wires.

  2. Using the graphic layout tool, make a simple combinational logic tree for the function F = AB + A'B'. Double-click to place a new module. There are many types of modules. We want to use a simple primitive logic gate, as shown below.

    Lay out two 2-input AND gates and one 2-input OR gate to build the circuit. Then connect the output of each AND gate to the inputs on the OR gate. You can click and drag to make wires.

    Create two input pins and one output pin, again by double-clicking and then selecting input or output from the pins category. Place the pins in the upper left (inputs) and upper right (outputs) of your graphical design. Then edit the names so the pins are named A, B, and F.

    Next, make a small wire coming out of each input pin and a small wire coming into the output pin. Label these as A, B, and F, respectively. By labeling wires you can make virtual connections between them.

    Next, add two NOT gates in front of the second AND gate and feed the A and B inputs to the NOT gates. The final circuit is shown below.

    Select File->Save Project and save your work as a bdf file.

  3. Compile the circuit by selecting Processing::Start compilation. Once complete, select Processing::Start::Start EDA_Netlist Writer. Now you are ready to start the simulation process.

    Select Tools::Run Simulation Tool::Gate Level Simulation. This should start ModelSim. If it does not, then you probably need to set the path to ModelSim. Do this by selecting Tool::Options. Then select the panel for EDA simulation tools. It has a line for ModelSim Altera. Enter the string:

    /opt/altera/11.1sp1/modelsim_ase/linux

    Once ModelSim is open, select Compile::Compile. Then select circui1.vho and click Compile. When the compilation is done, click Done to close the window.

    On the Transcript prompt, type vsim circuit1. This will create two new windows. Go back to the main window and select View::objects. Then detach the objects window, as below, leaving the waveform tab open on the main window.

    In the object window, right-click on object A (one of the input pins) and select Create Wave. We're going to make it a clock input that lasts for 1000ns with a period of 100ns. Make sure you have the units set correctly, as the default may be pico-seconds.

    Finish by specifying the clock to have the proper period (100ns). Repeat the process with object A, but make sure it has a period of 200ns. When you are done, right click in the wave window and select Zoom Full so you can see all of the waveforms.

    Now right-click on the F object and select Add::To Wave::Selected Signals. Finally, in the Transcript window, type run 1000ns. This should simluate the circuit and show you the resulting waveform of the output signal F.

    We'll cover pin assignments and programming the board next week.

When you have completed the lab assignment, go ahead and get started on the first project.