CS 232: Project #2

Project 2:

Main course page

Purpose: to give you more experience with digital design components.


  1. Create a circuit that takes in four bits and drives a 7 segment display for the hexadecimal characters 0-9,A-F. Make sure you differentiate the 6 and the b.
  2. Demonstrate the 7-segment driver circuit using an 8-bit counter that drives two seven segment displays. This will require you to include your 7-segment display driver into your top level design. Download this circuit onto the board. To see the numbers, you may want to use a 24- or 30-bit counter and use the highest 8-bits for display.

    Take a screen capture of your circuits and be prepared to demonstrate the circuit at the beginning of the next lab.

  3. Using either VHDL or graphic design, create a circuit that takes in two 4-bit binary numbers and outputs their sum as a 5-bit binary number. If you use the graphic design tool, you are free to use standard design elements from the Altera library. If you use VHDL, make use of the ieee.std_logic_arith package and make your inputs the type UNSIGNED.

    Use the 8 switches on the board to control the two inputs. Display the output on the board's 7-segment display as two hexadecimal digits. Note that the most significant digit will always be a 0 or 1, since the output of the circuit is only a 5-bit number. Double-check that the circuit works properly whether you interpret the 4-bit inputs as unsigned binary or 2's complement.

    Note that you will probably want to convert the two 4-bit inputs into 5-bit signals prior to executing the addition in VHDL. Then the result of the addition is a 5-bit signal you can assign to the output signal variable. The concatenation operator in VHDL is the ampersand: &. The following expression concatenates the bit '1' with the bit string "0010". The result would be the bit string "10010".

    '1 & "0010"

    Given two vector signals A and B that are type UNSIGNED (3 downto 0), you would add them as 5-bit numbers and assign them to a signal UNSIGNED (4 downto 0) using the following signal assignment statement.

    C <= ('0' & A) + ('0' & B);

    Take a screen capture of a waveform test of your final circuit (just showing 1-2 cases) and be prepared to demonstrate the circuit at the beginning of the next lab.



Create a wiki page with your writeup. For each task, write a short description of the task, in your own words.


Give your wiki page the label cs232S12project2.

Put your bdf/VHDL files in a folder called project2 in your private subdirectory on Academics/COMP/CS232.