CS 232: CPU Design

RISC CPU Design

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The register layout is shown in the graphic above. The instruction set is given below. It is modeled on the PowerPC RISC architecture, although the size and number of working registers is significantly reduced.

The instructions are 16 bits. All instructions have a 4-bit opcode in bits (15 downto 12). Most instructions then specify a source or destination register in the following 3 bits (11 downto 9). Other necessary registers and control flags follow. Instructions that use immediate values make use of the low 8 bits of the instruction to hold the immediate value.

InstructionopcodeRemaining bits
Load from RAM0000DDD-R-AAAAAAAA: DDD = dest (table B), R = add register E to immediate value, AAAAAAAA - immediate address value
Store to RAM0001SSS-R-AAAAAAAA: SSS = src (table B), R = add register E to immediate value, AAAAAAAA - immediate address value
Unconditional Branch0010UUUU-AAAAAAAA: U = unused, AAAAAAAA = immediate address value.
Conditional Branch0011CC-UU-AAAAAAAA: CC = condition (00 = zero, 01 = overflow, 10 = negative, 11 = carry), U = unused, AAAAAAAA = immediate address value.
Push0100SSS-UUUUUUUUU: SSS = src (table C) U = unused, operation puts the value into memory at location SP and increments SP.
Pop0101SSS-UUUUUUUUU: SSS = dest (table C) U = unused, operation reads the value from memory at location SP-1 and decrements SP.
Store to Output0110SSS-UUUUUUUUU: SSS = dest (table D) U = unused.
Load from Output0111SSS-UUUUUUUUU: SSS = dest (table B) U = unused.
Add1000SSS-DDD-TTT-UUU: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E)
Subtract1001SSS-DDD-TTT-UUU: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E)
And1010SSS-DDD-TTT-UUU: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E)
Or1011SSS-DDD-TTT-UUU: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E)
Exclusive-or1100SSS-DDD-TTT-UUU: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E)
Shift1101SSS-DDD-R-UUUUU: SSS = srcA (table E), DDD = dest (table B), R = direction bit '0' = left, '1' = right
Rotate1110SSS-DDD-R-UUUUU: SSS = srcA (table E), DDD = dest (table B), R = direction bit '0' = left, '1' = right
Move1111DDD-T-(IIIIIIII or SSS-UUUUU): DDD = dest (table B), T = if '1', treat low 8 bits as a sign-extended immediate value else SSS = source location (table D)

Below are the tables that show how to interpret the various register selection fields.

Table B
000Register A [RA]
001Register B [RB]
010Register C [RC]
011Register D [RD]
100Register E [RE]
101Stack Pointer [SP]
Table C
000Register A [RA]
001Register B [RB]
010Register C [RC]
011Register D [RD]
100Register E [RE]
101Stack Pointer [SP]
110Program Counter [PC]
111Condition Register [CR]
Table D
000Register A [RA]
001Register B [RB]
010Register C [RC]
011Register D [RD]
100Register E [RE]
101Stack Pointer [SP]
110Program Counter [PC]
111Instruction Register [IR]
Table E
000Register A [RA]
001Register B [RB]
010Register C [RC]
011Register D [RD]
100Register E [RE]
101Stack Pointer [SP]
110Zeros: "0000000000000000"
111Ones: "1111111111111111"

The ALU circuit takes in two source registers and an opcode, and it returns a destination value and a set of condition flags. The ALU opcodes correspond to the low three bits of the 4-bit opcode for instructions 1000 through 1111.

The condition register should be set by the ALU only for instructions at or above 1000: arithmetic, logical, and move instructions.