A Programmable Emulator for the Princeton IAS/Von Neumann Machine

Barry Fagin
Dale Skrien
Dept of Computer Science, US Air Force Academy
Dept. of Computer Science, Colby College
2354 Fairchild Drive
5851 Mayflower Hill
USAFA, CO 80840
Waterville, ME 04901-8858



IASSim is a Java application that emulates the Princeton IAS/Von Neumann machine. The IAS machine is described in the paper by Arthur W. Burks, Herman H. Goldstine, John von Neumann, entitled "Preliminary Discussion of the Logical Design of an Electronic Computing Instrument," written at the Institute for Advanced Study, Princeton, New Jersey, in June 1946. Copies of this paper can be found online at http://hdl.handle.net/2027.42/3972 (PDF and TXT versions) and http://www.cs.unc.edu/~adyilie/comp265/vonNeumann.html (HTML version). It was one of the first shared-memory computers (that is, instructions and data were both stored in memory).

IASSim is a free user-friendly, robust teaching tool suitable for undergraduate architecture and programming classes. . It permits users to write and run non-trivial programs in IAS assembly code or machine code. It is a fully-integrated development environment that includes the following features:

IASSim preserves the look and feel of the original machine. It was written using the Java Swing package. It should run on any platform that has the Java runtime environment, JRE version 1.5 or later, installed on it.

The new version 2 of IASSim includes a compiler for the high-level language JVNTRAN. JVNTRAN is a very simple high level language designed to be what a high level language would have been like for John Von Neumann’s IAS machine had such a language been available. JVNTRAN programs are created as text files and compiled by the emulator into IAS assembly language text files, which can then be assembled, loaded and executed on the simulated machine.

The IAS Architecture

The IAS machine is a machine with 4096 words of memory, each 40 bits wide. Each word can hold one 40-bit two's complement integer or two 20-bit machine instructions. A machine instruction consists of an 8-bit opcode followed by a 12-bit operand.

The IAS machine has 7 registers: Accumulator, Arithmetic Register, Control Counter, Control Register, Function Table Register, Memory Address Register, Selectron Register. The Accumulator and Arithmetic registers are the only two programmer-visible registers. The Control Counter is what we now call the Program Counter. The Control Register holds the currently executing instruction. The Function Table Register holds the current opcode, the Memory Address Register the current memory address, and the Selectron Register the current data value being read from or written to memory. The Accumulator, Arithmetic Register, and Selectron Register are 40 bits wide, the Control Register is 20 bits wide, the Function Table Register is 8 bits wide, and the other two registers are 12 bits wide.

The following table shows all the machine instructions. In this table, AC stands for the Accumulator register and AR stands for the Arithmetic register.

IAS Instruction Set
Instruction name Opcode Description
S(x)->Ac+ 1 copy the number in Selectron location x into AC
S(x)->Ac- 2 same as #1 but copy the negative of the number
S(x)->AcM 3 same as #1 but copy the absolute value
S(x)->Ac-M 4 same as #1 but subtract the absolute value
S(x)->Ah+ 5 add the number in Selectron location x into AC
S(x)->Ah- 6 subtract the number in Selectron location x from AC
S(X)->AhM 7 same as #5, but add the absolute value
S(X)->Ah-M 8 same as #7, but subtract the absolute value
S(x)->R 9 copy the number in Selectron location x into AR
R->A 10 copy the number in AR to AC
S(x)*R->A 11 Multiply the number in Selectron location x by the number in AR. Place the left half of the result in AC and the right half in AR.
A/S(x)->R 12 Divide the number in AC by the number in Selectron location x. Place the quotient in AR and the remainder in AC.
Cu->S(x) 13 Continue execution at the left-hand instruction of the pair at Selectron location x
Cu`->S(x) 14 Continue execution at the right-hand instruction of the pair at Selectron location x
Cc->S(x) 15 If the number in AC is >= 0, continue as in #13. Otherwise, continue normally.
Cc`->S(x) 16 If the number in AC is >= 0, continue as in #14. Otherwise, continue normally.
At->S(x) 17 Copy the number in AC to Selectron location x
Ap->S(x) 18 Replace the right-hand 12 bits of the left-hand instruction at Selectron location x by the right-hand 12 bits of the AC
Ap`->S(x) 19 Same as #18 but modifies the right-hand instruction
L 20 Shift the number in AC to the left 1 bit (new bit on the right is 0)
R 21 Shift the number in AC to the right 1 bit (leftmost bit is copied)
halt 0 Halt the program (see paragraph 6.8.5 of the IAS report)

Note that instructions 18 and 19 are used for indexing, which the IAS machine achieves through self-modifying code. Note also that the halt instruction is not part of the original set of instructions, but paragraph 6.8.5 of the report explains that there also needs to be an instruction that will tell the computer to halt, and so we included one.

The IAS machine does not include any instructions for handling I/O and so all data must be loaded into the Selectron memory directly before a program is executed.

IASSim Assembly Language Features

The IAS machine did not have an assembly language nor assembler, but we added a simple assembly language and assembler to the IASSim package to ease the development of programs for the IAS machine. The code below is a sample assembly language program.

    ; adds up the values n+...+3+2+1(+0) in a loop and stores
    ; the sum in memory at the location labeled "sum"
    loop:   S(x)->Ac+  n    ;load n into AC
            Cc->S(x)   pos  ;if AC >= 0, jump to pos
            halt            ;otherwise done
            .empty          ;a 20-bit 0
    pos:    S(x)->Ah+  sum  ;add n to the sum
            At->S(x)   sum  ;put total back at sum
            S(x)->Ac+  n    ;load n into AC
            S(x)->Ah-  one  ;decrement n
            At->S(x)   n    ;store decremented n
            Cu->S(x)   loop ;go back and do it again   

    n:     .data 5  ;will loop 6 times total
    one:   .data 1  ;constant for decrementing n
    sum:   .data 0  ;where the running/final total is kept

In this assembly language, labels are terminated with a colon, comments begin with a semicolon, and .data is a pseudoinstruction that converts its operand to a 40-bit binary number and stores it at the current memory location. The .empty pseudoinstruction is a placeholder for unused 20-bit half words. It stores a 20-bit zero at the indicated half word.

The following picture shows the IASSim application after the assembly program above has been loaded into the Selectron memory and the first two instructions have been executed. The row that is highlighted in the RAM Selectrons window corresponds to the highlighted line in the sum1toN.ias window. This line is the next instruction to be executed.

IAS Sim application



A sample JVNTRAN program is shown below. The compiler will translate this program into an assembly language program equivalent to the one above (although not as readable). For more about the language, read the JVNTRAN specification (which is also available from the Help menu in IASSim).

IAS Sim application



IASSim is freeware. You can download a 3 MB zip file containing the latest stable version (2.0.4) of the IASSim package. The installation instructions (which is also included in the zip file) explain how to install and start up the package. It runs under Java 1.5 or later. A User's Manual is available in the form of online help from the main menu and from buttons within the various dialog boxes of IASSim. The online manual includes a brief tutorial on getting started with IASSim.

Sample programming projects and their solutions are available for instructors. Please contact the authors if you are interested in these supplementary materials.


IASSim was developed as a frozen offshoot of the CPU Sim package in the spring and summer of 2010.

This page was last updated on March 17, 2012.