| Punctuation preferences | |
| Character | Use |
| ! | symbol |
| # | symbol |
| $ | symbol |
| % | symbol |
| & | symbol |
| ^ | symbol |
| _ | symbol |
| ` | symbol |
| * | symbol |
| ? | symbol |
| @ | symbol |
| ~ | symbol |
| + | symbol |
| - | symbol |
| ( | token |
| ) | token |
| , | token |
| / | token |
| = | token |
| [ | token |
| \ | token |
| ] | token |
| { | token |
| | | token |
| } | token |
| . | pseudo |
| : | label |
| ; | comment |
| Registers | |
| Name | Width |
| cpp | 32 |
| h | 32 |
| lv | 32 |
| mar | 32 |
| mbr | 8 |
| mdr | 32 |
| opc | 32 |
| pc | 32 |
| sp | 32 |
| status | 1 |
| tos | 32 |
| Register Arrays | ||
| Name | Length | Width |
| Condition Bits | |||
| Name | Register | Bit | Halt |
| halt-bit | status | 0 | true |
| RAMs | |
| Name | Length |
| ConstantPool | 256 |
| Main | 256 |
| Stack | 256 |
| Set | ||||
| Name | Register | Start Bit | Number of Bits | Value |
| mar=0 | mar | 0 | 32 | 0 |
| mdr=-1 | mdr | 0 | 32 | -1 |
| mdr=0 | mdr | 0 | 32 | 0 |
| mdr=1 | mdr | 0 | 32 | 1 |
| pc=0 | pc | 0 | 32 | 0 |
| Test | ||||||
| Name | Register | Start Bit | Number of Bits | Comparison | Value | Omission |
| mar!=0?skip1 | mar | 0 | 32 | NE | 0 | 1 |
| mdr<0?skip2 | mdr | 0 | 32 | LT | 0 | 2 |
| mdr=0?skip2 | mdr | 0 | 32 | EQ | 0 | 2 |
| sp<0?skip2 | sp | 0 | 32 | LT | 0 | 2 |
| Increment | |||
| Name | Register | Overflow Bit | Delta |
| dec1-pc | pc | halt-bit | -1 |
| dec4-sp | sp | halt-bit | -4 |
| inc1-pc | pc | halt-bit | 1 |
| inc2-pc | pc | halt-bit | 2 |
| inc3-pc | pc | halt-bit | 3 |
| inc4-pc | pc | halt-bit | 4 |
| inc4-sp | sp | halt-bit | 4 |
| Shift | |||||
| Name | Source | Destination | Type | Direction | Distance |
| mar<<2 | mar | mar | logical | left | 2 |
| mdr<<2 | mdr | mdr | logical | left | 2 |
| mdr<<8 | mdr | mdr | logical | left | 8 |
| mdr>>24 | mdr | mdr | logical | right | 24 |
| mdr>>>16 | mdr | mdr | arithmetic | right | 16 |
| mdr>>>24 | mdr | mdr | arithmetic | right | 24 |
| Logical | ||||
| Name | Type | Source1 | Source2 | Destination |
| mdr<-mdr&h | AND | mdr | h | mdr |
| mdr<-mdr|h | OR | mdr | h | mdr |
| Arithmetic | ||||||
| Name | Type | Source1 | Source2 | Destination | Overflow Bit | Carry Bit |
| mar=mar-sp | SUBTRACT | mar | sp | mar | halt-bit | (none) |
| mdr=mdr*h | MULTIPLY | mdr | h | mdr | halt-bit | (none) |
| mdr=mdr+h | ADD | mdr | h | mdr | halt-bit | (none) |
| mdr=mdr+tos | ADD | mdr | tos | mdr | halt-bit | (none) |
| mdr=mdr-h | SUBTRACT | mdr | h | mdr | halt-bit | (none) |
| mdr=mdr/h | DIVIDE | mdr | h | mdr | halt-bit | (none) |
| pc=mdr+pc | ADD | pc | mdr | pc | halt-bit | (none) |
| Branch | |
| Name | Amount |
| branch+3 | 3 |
| branch+5 | 5 |
| TransferRtoR | |||||
| Name | Source | Src Start Bit | Destination | Dest Start Bit | Number of Bits |
| h->mdr | h | 0 | mdr | 0 | 32 |
| lv->h | lv | 0 | h | 0 | 32 |
| mdr->h | mdr | 0 | h | 0 | 32 |
| mdr->mar | mdr | 0 | mar | 0 | 32 |
| mdr->opc | mdr | 0 | opc | 0 | 32 |
| mdr->tos | mdr | 0 | tos | 0 | 32 |
| mdr0-16->mar | mdr | 0 | mar | 16 | 16 |
| mdr0-16->pc | mdr | 0 | pc | 16 | 16 |
| opc->mdr | opc | 0 | mdr | 0 | 32 |
| pc->mar | pc | 0 | mar | 0 | 32 |
| tos->h | tos | 0 | h | 0 | 32 |
| tos->mdr | tos | 0 | mdr | 0 | 32 |
| TransferRtoA | ||||||||
| Name | Source | Src Start Bit | Destination | Dest Start Bit | Number of Bits | Index | Index Start Bit | Index Number of Bits |
| TransferAtoR | ||||||||
| Name | Source | Src Start Bit | Destination | Dest Start Bit | Number of Bits | Index | Index Start Bit | Index Number of Bits |
| Decode | |
| Name | IR |
| decode | mbr |
| Set Condition Bit | ||
| Name | Bit | Value |
| setHalt | halt-bit | 1 |
| IO | ||||
| Name | Direction | Type | Buffer | Connection |
| mdr->output | output | integer | mdr | [Console] |
| mdr<-input | input | integer | mdr | [Console] |
| Memory Access | ||||
| Name | Direction | Memory | Data | Address |
| mbr<-Main[pc] | read | Main | mbr | pc |
| mdr->Main[mar] | write | Main | mdr | mar |
| mdr->Stack[mar] | write | Stack | mdr | mar |
| mdr->Stack[sp] | write | Stack | mdr | sp |
| mdr<-CP[mar] | read | ConstantPool | mdr | mar |
| mdr<-Main[mar] | read | Main | mdr | mar |
| mdr<-Stack[mar] | read | Stack | mdr | mar |
| mdr<-Stack[sp] | read | Stack | mdr | sp |
| EQUs | |
| Name | Value |
| Instruction Format Fields | ||||||
| Name | Type | Number of Bits | Relativity | Signed | Default Value | Values |
| relAddr16 | required | 16 | pcRelativePreIncr | true | 0 | <any> |
| sgn8 | required | 8 | absolute | true | 0 | <any> |
| indx | required | 8 | absolute | false | 0 | <any> |
| op | required | 8 | absolute | false | 0 | <any> |
| 1 | required | 1 | absolute | true | 0 | <any> |
| -1 | ignored | 1 | absolute | true | 0 | <any> |
| 2 | required | 2 | absolute | true | 0 | <any> |
| -2 | ignored | 2 | absolute | true | 0 | <any> |
| 3 | required | 3 | absolute | true | 0 | <any> |
| -3 | ignored | 3 | absolute | true | 0 | <any> |
| 4 | required | 4 | absolute | true | 0 | <any> |
| -4 | ignored | 4 | absolute | true | 0 | <any> |
| 5 | required | 5 | absolute | true | 0 | <any> |
| -5 | ignored | 5 | absolute | true | 0 | <any> |
| 6 | required | 6 | absolute | true | 0 | <any> |
| -6 | ignored | 6 | absolute | true | 0 | <any> |
| 7 | required | 7 | absolute | true | 0 | <any> |
| -7 | ignored | 7 | absolute | true | 0 | <any> |
| 8 | required | 8 | absolute | true | 0 | <any> |
| -8 | ignored | 8 | absolute | true | 0 | <any> |
| 9 | required | 9 | absolute | true | 0 | <any> |
| -9 | ignored | 9 | absolute | true | 0 | <any> |
| 10 | required | 10 | absolute | true | 0 | <any> |
| -10 | ignored | 10 | absolute | true | 0 | <any> |
| 11 | required | 11 | absolute | true | 0 | <any> |
| -11 | ignored | 11 | absolute | true | 0 | <any> |
| 12 | required | 12 | absolute | true | 0 | <any> |
| -12 | ignored | 12 | absolute | true | 0 | <any> |
| 13 | required | 13 | absolute | true | 0 | <any> |
| -13 | ignored | 13 | absolute | true | 0 | <any> |
| 14 | required | 14 | absolute | true | 0 | <any> |
| -14 | ignored | 14 | absolute | true | 0 | <any> |
| 15 | required | 15 | absolute | true | 0 | <any> |
| -15 | ignored | 15 | absolute | true | 0 | <any> |
| 16 | required | 16 | absolute | true | 0 | <any> |
| -16 | ignored | 16 | absolute | true | 0 | <any> |
| Fetch Sequence |
| Microinstructions |
|
mbr<-Main[pc] inc1-pc decode |
| Machine Instructions | |||
| Name | Opcode (hex) | Format | Microinstructions |
| iinc | 84 | op indx sgn8 | pc->mar mdr<-Main[mar] mdr->opc mdr>>24 mdr<<2 lv->h mdr=mdr+h mdr->mar mdr<-Stack[mar] mdr->h opc->mdr mdr<<8 mdr>>>24 mdr=mdr+h mdr->Stack[mar] inc2-pc mar=mar-sp mar!=0?skip1 mdr->tos End |
| istore | 36 | op indx | mdr<-Stack[sp] mdr->opc dec4-sp pc->mar mdr<-Main[mar] mdr>>24 mdr<<2 lv->h mdr=mdr+h mdr->mar opc->mdr mdr->Stack[mar] mdr<-Stack[sp] mdr->tos inc1-pc End |
| iload | 15 | op indx | pc->mar mdr<-Main[mar] mdr>>24 mdr<<2 lv->h mdr=mdr+h mdr->mar mdr<-Stack[mar] inc4-sp mdr->Stack[sp] mdr->tos inc1-pc End |
| ifeq | 99 | op relAddr16 | tos->mdr dec4-sp mdr=0?skip2 inc2-pc branch+5 pc->mar mdr<-Main[mar] dec1-pc mdr>>>16 pc=mdr+pc mdr<-Stack[sp] mdr->tos End |
| iflt | 9B | op relAddr16 | tos->mdr dec4-sp mdr<0?skip2 inc2-pc branch+5 pc->mar mdr<-Main[mar] mdr>>>16 dec1-pc pc=mdr+pc mdr<-Stack[sp] mdr->tos End |
| if_icmpeq | 9F | op relAddr16 | tos->h dec4-sp mdr<-Stack[sp] dec4-sp mdr=mdr-h mdr=0?skip2 inc2-pc branch+5 pc->mar mdr<-Main[mar] dec1-pc mdr>>>16 pc=mdr+pc mdr<-Stack[sp] mdr->tos End |
| dup_x2 | 5B | op | inc4-sp tos->mdr mdr->Stack[sp] dec4-sp dec4-sp mdr<-Stack[sp] inc4-sp mdr->Stack[sp] dec4-sp dec4-sp mdr<-Stack[sp] inc4-sp mdr->Stack[sp] dec4-sp tos->mdr mdr->Stack[sp] inc4-sp inc4-sp inc4-sp End |
| idiv | 6C | op | tos->h dec4-sp mdr<-Stack[sp] mdr=mdr/h mdr->tos mdr->Stack[sp] End |
| imul | 68 | op | tos->h dec4-sp mdr<-Stack[sp] mdr=mdr*h mdr->tos mdr->Stack[sp] End |
| isub | 64 | op | tos->h dec4-sp mdr<-Stack[sp] mdr=mdr-h mdr->tos mdr->Stack[sp] End |
| ior | 80 | op | tos->h dec4-sp mdr<-Stack[sp] mdr<-mdr|h mdr->tos mdr->Stack[sp] End |
| iand | 7E | op | tos->h dec4-sp mdr<-Stack[sp] mdr<-mdr&h mdr->tos mdr->Stack[sp] End |
| ldc_w | 13 | op 16 | inc4-sp pc->mar mdr<-Main[mar] mar=0 mdr0-16->mar mar<<2 mdr<-CP[mar] mdr->Stack[sp] mdr->tos End |
| nop | 00 | op | End |
| swap | 5F | op | dec4-sp mdr<-Stack[sp] mdr->h inc4-sp mdr->Stack[sp] dec4-sp tos->mdr mdr->Stack[sp] inc4-sp h->mdr mdr->tos End |
| pop | 57 | op | dec4-sp mdr<-Stack[sp] mdr->tos End |
| dup_x1 | 5A | op | tos->mdr inc4-sp mdr->Stack[sp] dec4-sp dec4-sp mdr<-Stack[sp] inc4-sp mdr->Stack[sp] dec4-sp tos->mdr mdr->Stack[sp] inc4-sp inc4-sp End |
| dup | 59 | op | tos->mdr inc4-sp mdr->Stack[sp] End |
| goto | A7 | op relAddr16 | pc->mar mdr<-Main[mar] dec1-pc mdr>>>16 pc=mdr+pc End |
| exit | FC | op | setHalt End |
| iconst_0 | 03 | op | mdr=0 inc4-sp mdr->Stack[sp] mdr->tos End |
| iconst_-1 | 02 | op | mdr=-1 inc4-sp mdr->Stack[sp] mdr->tos End |
| iconst_1 | 04 | op | mdr=1 inc4-sp mdr->Stack[sp] mdr->tos End |
| output | FF | op | mdr<-Stack[sp] dec4-sp mdr->output sp<0?skip2 mdr<-Stack[sp] mdr->tos End |
| input | FE | op | mdr<-input inc4-sp mdr->Stack[sp] mdr->tos End |
| iadd | 60 | op | tos->h dec4-sp mdr<-Stack[sp] mdr=mdr+h mdr->tos mdr->Stack[sp] End |