JVM2

Registers
Name	Width
cpp	32
h	32
heap	32
lv	32
mar	32
mbr	8
mdr	32
opc	32
pc	32
sp	32
status	1
tos	32

Register Arrays
Name	Length	Width
(none)

Condition Bits
Name	Register	Bit	Halt
halt-bit	status	0	true

RAMs
Name	Length
ConstantPool	128
Main	128
Stack	256

Set
Name	Register	Start Bit	Number of Bits	Value
mar=0	mar	0	32	0
mdr=-1	mdr	0	32	-1
mdr=0	mdr	0	32	0
mdr=1	mdr	0	32	1
pc=0	pc	0	32	0

Test
Name	Register	Start Bit	Number of Bits	Comparison	Value	Omission
mar!=0?skip1	mar	0	32	NE	0	1
mdr<0?skip2	mdr	0	32	LT	0	2
mdr=0?skip2	mdr	0	32	EQ	0	2
sp<0?skip2	sp	0	32	LT	0	2

Increment
Name	Register	Overflow Bit	Delta
dec4-sp	sp	halt-bit	-4
inc1-pc	pc	halt-bit	1
inc2-pc	pc	halt-bit	2
inc3-pc	pc	halt-bit	3
inc4-mar	mar	halt-bit	4
inc4-pc	pc	halt-bit	4
inc4-sp	sp	halt-bit	4

Shift
Name	Source	Destination	Type	Direction	Distance
mar<<2	mar	mar	logical	left	2
mdr<<2	mdr	mdr	logical	left	2
mdr<<8	mdr	mdr	logical	left	8
mdr>>24	mdr	mdr	arithmetic	right	24
mdr>>>16	mdr	mdr	logical	right	16
mdr>>>24	mdr	mdr	logical	right	24

Logical
Name	Type	Source1	Source2	Destination
mdr<-mdr&h	AND	mdr	h	mdr
mdr<-mdr|h	OR	mdr	h	mdr

Arithmetic
Name	Type	Source1	Source2	Destination	Overflow Bit	Carry Bit
mar=mar-sp	SUBTRACT	mar	sp	mar	halt-bit	(none)
mdr=mdr*h	MULTIPLY	mdr	h	mdr	halt-bit	(none)
mdr=mdr+h	ADD	mdr	h	mdr	halt-bit	(none)
mdr=mdr+opc	ADD	mdr	opc	mdr	halt-bit	(none)
mdr=mdr+tos	ADD	mdr	tos	mdr	halt-bit	(none)
mdr=mdr-h	SUBTRACT	mdr	h	mdr	halt-bit	(none)
mdr=mdr/h	DIVIDE	mdr	h	mdr	halt-bit	(none)

Branch
Name	Amount
branch+3	3

TransferRtoR
Name	Source	Src Start Bit	Destination	Dest Start Bit	Number of Bits
h->mdr	h	0	mdr	0	32
lv->h	lv	0	h	0	32
lv->mar	lv	0	mar	0	32
lv->sp	lv	0	sp	0	32
mdr->h	mdr	0	h	0	32
mdr->lv	mdr	0	lv	0	32
mdr->mar	mdr	0	mar	0	32
mdr->opc	mdr	0	opc	0	32
mdr->pc	mdr	0	pc	0	32
mdr->sp	mdr	0	sp	0	32
mdr->tos	mdr	0	tos	0	32
mdr0-16->mar	mdr	0	mar	16	16
mdr0-16->pc	mdr	0	pc	16	16
opc->mdr	opc	0	mdr	0	32
pc->mar	pc	0	mar	0	32
pc->mdr	pc	0	mdr	0	32
sp->mdr	sp	0	mdr	0	32
tos->h	tos	0	h	0	32
tos->mdr	tos	0	mdr	0	32
tos->pc	tos	0	pc	0	32

TransferRtoA
Name	Source	Src Start Bit	Destination	Dest Start Bit	Number of Bits	Index	Index Start Bit	Index Number of Bits
(none)

TransferAtoR
Name	Source	Src Start Bit	Destination	Dest Start Bit	Number of Bits	Index	Index Start Bit	Index Number of Bits
(none)

Decode
Name	IR
decode	mbr

Set Condition Bit
Name	Bit	Value
setHalt	halt-bit	1

IO
Name	Direction	Type	Buffer	Connection
mdr->output	output	integer	mdr	[Console]
mdr<-input	input	integer	mdr	[Console]

Memory Access
Name	Direction	Memory	Data	Address
mbr<-Main[pc]	read	Main	mbr	pc
mdr->Main[mar]	write	Main	mdr	mar
mdr->Stack[mar]	write	Stack	mdr	mar
mdr->Stack[sp]	write	Stack	mdr	sp
mdr<-CP[mar]	read	ConstantPool	mdr	mar
mdr<-Main[mar]	read	Main	mdr	mar
mdr<-Stack[mar]	read	Stack	mdr	mar
mdr<-Stack[sp]	read	Stack	mdr	sp

EQUs
Name	Value
(none)

Fetch Sequence

Microinstructions

mbr<-Main[pc] inc1-pc decode

Machine Instructions
Name	Opcode (hex)	Field Lengths	Microinstructions
ireturn	AC	8	End
return	B1	8	lv->sp dec4-sp lv->mar mdr<-Stack[mar] mdr->mar mdr<-Stack[mar] mdr->pc inc4-mar mdr<-Stack[mar] mdr->lv sp<0?skip2 mdr<-Stack[sp] mdr->tos End
invokev	B6	8  16	pc->mar mdr<-Main[mar] mdr>>>16 mdr->tos mdr->mar mdr<-Main[mar] mdr->opc mdr>>>24 mdr->h opc->mdr mdr<<8 mdr>>>24 mdr->opc mdr=mdr-h mdr<<2 mdr->h sp->mdr mdr=mdr+h mdr->sp inc4-sp opc->mdr mdr<<2 mdr->h sp->mdr mdr=mdr-h mdr->mar mdr->opc sp->mdr mdr->Stack[mar] inc2-pc pc->mdr mdr->Stack[sp] lv->h h->mdr inc4-sp mdr->Stack[sp] opc->mdr mdr->lv tos->pc inc2-pc mdr<-Stack[sp] mdr->tos End
iinc	84	8  8  8	pc->mar mdr<-Main[mar] mdr->opc mdr>>>24 mdr<<2 lv->h mdr=mdr+h mdr->mar mdr<-Stack[mar] mdr->h opc->mdr mdr<<8 mdr>>24 mdr=mdr+h mdr->Stack[mar] inc2-pc mar=mar-sp mar!=0?skip1 mdr->tos End
istore	36	8  8	pc->mar inc1-pc mdr<-Main[mar] mdr>>>24 mdr<<2 lv->h mdr=mdr+h mdr->mar tos->mdr mdr->Stack[mar] dec4-sp sp<0?skip2 mdr<-Stack[sp] mdr->tos End
iload	15	8  8	pc->mar mdr<-Main[mar] mdr>>>24 mdr<<2 lv->h mdr=mdr+h mdr->mar mdr<-Stack[mar] inc4-sp mdr->Stack[sp] mdr->tos inc1-pc End
bipush	10	8  8	pc->mar mdr<-Main[mar] mdr>>24 inc4-sp mdr->Stack[sp] mdr->tos inc1-pc End
ifeq	99	8  16	tos->mdr dec4-sp mdr=0?skip2 inc2-pc branch+3 pc->mar mdr<-Main[mar] mdr0-16->pc sp<0?skip2 mdr<-Stack[sp] mdr->tos End
iflt	9B	8  16	tos->mdr dec4-sp mdr<0?skip2 inc2-pc branch+3 pc->mar mdr<-Main[mar] mdr0-16->pc sp<0?skip2 mdr<-Stack[sp] mdr->tos End
if_icmpeq	9F	8  16	tos->h dec4-sp mdr<-Stack[sp] dec4-sp mdr=mdr-h mdr=0?skip2 inc2-pc branch+3 pc->mar mdr<-Main[mar] mdr0-16->pc sp<0?skip2 mdr<-Stack[sp] mdr->tos End
dup_x2	5B	8	inc4-sp tos->mdr mdr->Stack[sp] dec4-sp dec4-sp mdr<-Stack[sp] inc4-sp mdr->Stack[sp] dec4-sp dec4-sp mdr<-Stack[sp] inc4-sp mdr->Stack[sp] dec4-sp tos->mdr mdr->Stack[sp] inc4-sp inc4-sp inc4-sp End
idiv	6C	8	tos->h dec4-sp mdr<-Stack[sp] mdr=mdr/h mdr->tos mdr->Stack[sp] End
imul	68	8	tos->h dec4-sp mdr<-Stack[sp] mdr=mdr*h mdr->tos mdr->Stack[sp] End
isub	64	8	tos->h dec4-sp mdr<-Stack[sp] mdr=mdr-h mdr->tos mdr->Stack[sp] End
ior	80	8	tos->h dec4-sp mdr<-Stack[sp] mdr<-mdr|h mdr->tos mdr->Stack[sp] End
iand	7E	8	tos->h dec4-sp mdr<-Stack[sp] mdr<-mdr&h mdr->tos mdr->Stack[sp] End
ldc_w	13	8  16	inc4-sp pc->mar mdr<-Main[mar] mar=0 mdr0-16->mar mar<<2 mdr<-CP[mar] mdr->Stack[sp] mdr->tos End
nop	00	8	End
swap	5F	8	dec4-sp mdr<-Stack[sp] mdr->h inc4-sp mdr->Stack[sp] dec4-sp tos->mdr mdr->Stack[sp] inc4-sp h->mdr mdr->tos End
pop	57	8	dec4-sp sp<0?skip2 mdr<-Stack[sp] mdr->tos End
dup_x1	5A	8	tos->mdr inc4-sp mdr->Stack[sp] dec4-sp dec4-sp mdr<-Stack[sp] inc4-sp mdr->Stack[sp] dec4-sp tos->mdr mdr->Stack[sp] inc4-sp inc4-sp End
dup	59	8	tos->mdr inc4-sp mdr->Stack[sp] End
goto	A7	8  16	pc->mar mdr<-Main[mar] pc=0 mdr0-16->pc End
stop	FC	8	setHalt End
iconst_0	03	8	mdr=0 inc4-sp mdr->Stack[sp] mdr->tos End
iconst_-1	02	8	mdr=-1 inc4-sp mdr->Stack[sp] mdr->tos End
iconst_1	04	8	mdr=1 inc4-sp mdr->Stack[sp] mdr->tos End
output	FF	8	tos->mdr mdr->output dec4-sp sp<0?skip2 mdr<-Stack[sp] mdr->tos End
input	FE	8	mdr<-input inc4-sp mdr->Stack[sp] mdr->tos End
iadd	60	8	tos->h dec4-sp mdr<-Stack[sp] mdr=mdr+h mdr->tos mdr->Stack[sp] End