-- Bruce A. Maxwell
-- Spring 2016
-- CS 232 Project 6
--
-- test program for the memory circuit
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ramromtester is
end entity;

architecture test of ramromtester is
  constant num_cycles : integer := 160;

  -- this circuit just needs a clock and a reset
  signal clk : std_logic := '1';
  signal reset : std_logic;

  -- lights component
  component ramtest
    port( clk, reset : in std_logic;
          data     : out std_logic_vector(7 downto 0);
          ram_input_view : out std_logic_vector(7 downto 0);
          state_view : out std_logic_vector(3 downto 0);
          ram_addr_view : out std_logic_vector(3 downto 0);
          rom_addr_view : out std_logic_vector(3 downto 0);
          we_view: out std_logic
          );
  end component;

  -- output signals
  signal lightsig : std_logic_vector(7 downto 0);
  signal stateview : std_logic_vector(3 downto 0);
  signal ramaddrview : std_logic_vector(3 downto 0);
  signal romaddrview : std_logic_vector(3 downto 0);
  signal raminputview : std_logic_vector(7 downto 0);
  signal we_view : std_logic;

begin

  -- start off with a short reset
  reset <= '0', '1' after 5 ns;

  -- create a clock
  process begin
    for i in 1 to num_cycles loop
      clk <= not clk;
      wait for 5 ns;
      clk <= not clk;
      wait for 5 ns;
    end loop;
    wait;
  end process;

  -- port map the circuit
  L0: ramtest port map( clk, reset, lightsig, raminputview, stateview, ramaddrview, romaddrview, we_view );

end test;