-- Bruce A. Maxwell
-- Spring 2016
-- CS 232
--
-- test program for the counter
-- shows how to create a clock using a loop

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clockbench is
end entity;

architecture test of clockbench is
  constant num_cycles : integer := 40;  -- run for 40 clock cycles

  -- this circuit needs a clock, enable, and a reset
  signal clk : std_logic := '1';
  signal enable : std_logic;
  signal reset : std_logic;

  -- counter component
  component counter
	port
	(
		clk		  : in std_logic;
		reset	  : in std_logic;
		enable	  : in std_logic;
		q		  : out std_logic_vector (3 downto 0)
	);
  end component;

  -- output signals
  signal val : std_logic_vector (3 downto 0);

begin

  -- start off with a short reset
  reset <= '1', '0' after 5 ns;

  enable <= '1';

  -- create a clock
  process begin
    for i in 1 to num_cycles loop
      clk <= not clk;
      wait for 5 ns;
      clk <= not clk;
      wait for 5 ns;
    end loop;
    wait;
  end process;

  -- port map the circuit
  L0: counter port map( clk, reset, enable, val );

end test;