CS 232: Lab 1

Lab 1: Digital Logic CAD Tools

The purpose of this lab is to familiarize you with logic gates and basic digital logic design techniques. We will be using a digital logic CAD program, Quartus, to generate our designs using a graphic layout tool. We will use a simulation tool, ghdl, to test our designs and ensure they are working correctly. Finally, those of us on campus will download the program to a FPGA board to see it in action. Those of us off-campus will use a second simulation tool to visualize the board.

If you want to watch a movie of the first 40 minutes of the lab Zoom session, please do so here.

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Design a Circuit using Quartus

1. If you are off-campus, then you will need to access the virtual machines using Apporto

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   1. Go to colby.apporto.com and log in with your Colby username and password. Then launch the Linux Desktop.

      

   2. Accept the default settings for the next several screens.
   3. Now you are ready to use virtual machine.

      At the top is a white bar with buttons. Those are for interacting with Apporto, the software that allows you to make the virtual machine.

      Most of the screen is the virtual Linux box that we will be using. The two most important applications we will be using are the Terminal and the Firefox web browser. The third application we will be using today is quartus, which we need to start from the Terminal (instructions below).

      To switch between applications, you can go to the Activities label in the top left corner.

      To log out, log out of the virtual box using the button circled in blue.

      Copy-pasting is tricky.

      • If you want to copy-paste from on application within the virtual box to another, Ctrl-C (not command-C) should copy and Shift-Ctrl-C should paste.
      • The only way I have figured out how to paste into an Apporto window from another application on my machine is to use the Paste option in the Edit menu of the browser(not the application you are pasting in).

      Downloading is also tricky. I follow the link to the file, which opens it in another tab, then press the menu button on the right (three bars, circled in red below), and use Save Page As to choose the appropriate directory.

      

   Start Quartus by opening a terminal and typing:

   quartus

   If that doesn't work, you may need to give it a full path name: /export/local/bin/quartus

   If you want to put quartus in the background, add an ampersand (&) to the end of the command line.

   The first time you open Quartus, it will prompt you for a license. Indicate that you have a license file, then enter /export/opt/altera/12.1/license.dat in the dialog box that appears.

   Quartus should start up and display a window with the option of creating a new project, opening an interactive tutorial, or opening an existing project. It might be a good idea to go through the tutorial on your own time.

   

   Specify where you want to put the project and a name for it and the top level design entity. As noted, the project name and entity name must be identical. You should put each project in its own sub-directory, probably inside a cs232 folder.

   

   We have no design files to add, so skip the next screen.

   If you are just simulating, let the device be selected automatically. If you want to use an FPGA board, you will have to set this to the device on the board.

   If are in Davis 122, select the device for the DE1 board, which is a Cyclone II FPGA with the name EP2C20F484C7. If not, just press the Next button
   

   In the EDA Tool settings, set the Simulation entry to ModelSim-Altera with the format VHDL. That should complete your project setup.

   After creating the project, select File::New and pick a Block Diagram/Schematic File.

   

   In the block diagram file you can now lay out circuits graphically and connect them with virtual wires.

2. Using the graphic layout tool, make a simple combinational logic tree for the function F = AB + A'B'. Double-click on the dotted background or press the button above that looks like an AND gate to place a new module. There are many types of modules. We want to use a simple primitive logic gate, as shown below.

   

   Lay out two 2-input AND gates and one 2-input OR gate to build the circuit. Then connect the output of each AND gate to the inputs on the OR gate. You can click and drag to make wires.

   

   Create two input pins and one output pin, again by double-clicking and then selecting input or output from the pins category. Place the pins in the upper left (inputs) and upper right (outputs) of your graphical design. Then edit the names so the pins are named A, B, and F.

   Next, make a small wire coming out of each input pin and a small wire coming into the output pin. A really helpful feature of Quartus is that is allows yout to label wires. This makes virtual connections, so you don't need to have lots of crossing lines. To label a wire, simply type while it is selected. Label these as A, B, and F, respectively.

   Next, add two NOT gates in front of the second AND gate and feed the A and B inputs to the NOT gates. The final circuit is shown below.

   

   Select File->Save Project and save your work as a bdf file. Since it is the top level file in your project, give it the same name as your project name, in this case circuit1.bdf.

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Model a Circuit Using GHDL

Our first goal will be to simulate the circuit. First, we convert the circuit diagram to VHDL file. VHDL is a programming language designed for simulating circuits, and you will learn it in coming weeks. Then, we use the ghdl command line tool to run the simulation.

1. Select File::Create/Update::Create HDL Design File from Curent File.

In the popup, select VHDL and click Ok. This should create a vhdl file version of your circuit. The name of the file will end in .vhd

2. Now you need to create a driver file that sends signals into your circuit and accepts the output. An example for the circuit above is testbench.vhd. This file defines three signals: A, B, and F. It then assigns values to A and B at certain time intervals. These values and time intervals form the four possible combinations of A and B. The file then attaches these signals to the circuit you created above. Note that you will need to edit the testbench.vhd file so the component statement label matches the name of the circuit you created. I named mine test, so my version needs to say "component test" in the declaration section and "test port map" in the code section. If your file is named circuit1, then your file needs to say "component circuit1" in the declaration section and "circuit1 port map" in the code section.
3. Save your VHDL test bench file in the same directory with your circuit's vhdl file.

Note: If you are in Davis 122, the computers have issues with file permissions. You probably won't be able to right-click and save. Instead, you will need to follow the link to the file, select is all, copy it, then create a new file in Quartus, paste into it, then save it.

4. Run the ghdl tool to compile the code, produce a simulation output (a .vcd file), and then view each signal over time with gktwave.

   The instructions are in this movie and below:

   1. Run the ghdl tool in the Terminal (making sure you are in the same directory as the .vhd files) to compile and simulate your circuit. Remember, I called my circuit circuit1, so my vhdl file is called circuit1.vhd.

      ghdl -a circuit1.vhd testbench.vhd
      ghdl -e testbench
      ghdl -r testbench --vcd=testbench.vcd
      

   2. Finally, open up the .vcd file in gtkwave.

      gtkwave testbench.vcd

      Once the window opens, select all of your signals and select "Insert". Then click on the "Zoom to Fit" button or set the bounds of the window to 0 ns to 100 ns. You should end up with a visualization like below.

      You can see in this example that the circuit is working properly. The output F is high when A and B are both low (0) or both high (1), and F is low (0) when A and B are not the same value.

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Test a Circuit with the Altera DE1 Board

If you are on campus and using a board, follow these instructions. Otherwise, jump down to the vcd animation instructions.

The Altera DE1 board contains a programmable Field Programmable Gate Array [FPGA]. An FPGA is an electronically configurable set of gates (truth tables) that can be programmed to emulate very complex digital circuits, including CPUs. The Quartus software can compile a digital circuit into a form that can be downloaded onto the FPGA.

The Altera DE1 board contains many different input and output devices, including push-buttons, switches, LEDs, and 7-segment displays. We will be using these input and output devices to control and evaluate our circuits.

You can find the documentation for the DE1 board here. Pages 26-30 specify which output pins control which I/O devices.

In order to program the board, you need to follow these steps.

1. Compile the code with Quartus (Quartus compiles the code for download onto the board, whereas ghdl compiled it for simulation). Press the purple arrow to do so.

   

2. Open up the Assignment:Pin Planner window. If you have set up the input and output pins of your circuit correctly, they will show up at the bottom of the window. In the Location column, specify the pin for each input and output. For the simple circuit above, for example, you can use the first two switches (PIN_L21 and PIN_L22) as the inputs and the first red LED (PIN_R20) as the output.

   Once you have specified the pins for all inputs and outputs, close the Pin Planner window and compile your circuit. Any time you change pin assignments, you must recompile.

3. Second, plug the DE1 board into an available USB port, if it is not already plugged in. If no lights appear, then click the red button to turn on the board. The default program should produce flashing lights.
4. Third, open up the Tools::Programmer window. If the window says "No Hardware" then click on Hardware Setup, click on the popup menu that says "No Hardware" and select the USB Blaster. Then close the Hardware Setup window.

   At this point, if the Start button is available, click it and it should program the board. If the Start button is not active, then click Select File, navigate to your output_files directory and select the .sof file corresponding to your circuit. If the Start button is now active, click Start and it should program the board. You will know the board has been programmed when the default FPGA program with the flashing lights stops.

   If clicking on the Start button does nothing, please contact me and let me know the (1) name of the machine on which you are working and (2) whether any error messages show up in the Quartus log window.

5. Once the board is programmed, you can control your circuit by modifying the switches you set up to control the circuit inputs. In the case of the simple circuit above, if the two switches are both 0 or both 1, then the LED should light up.

   Here is a demo

6. When you are done with the board, please use the red button to turn it off.

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Make an Animation of the Board from the Simulation Output

We will make an animation of the simulation output. This is not required for students on-campus, but it may be worth your time learning how to use the tool.

Our goal is to make an animation that shows what the board would be doing if you were controlling it with the inputs defined in the test-driver (testbench.vhd). Stephanie wrote a Python program to animate inputs (switches and key button) and outputs (LEDs and 7-segment displays). To use that program, you need the .vcd file that was generated by ghdl. This tells us what values the signals have at each point in time. You will also need to define which signals are mapped to which elements on the board.

1. Start by watching a movie demonstrating how to do this.

Not all elements of the board are used in this lab, but they will be eventually. They include 7-segment displays (like in a digital clock), switches, green and red LEDs, and buttons (which I label as "key buttons" because the DE1 board documentation names them key0, key1, etc..


2. Next, make a file named testbench.txt in the same directory as testbench.vcd. You can use Quartus as your editor or a simpler program (e.g. vi). Map signal A to the switch that is second-from-the-right, signal B to the rightmost switch, and signal F to the rightmost red LED. The contents of the file are

   # signal name, bit in signal, type of board widget, which bit in board widget
   A,0,switch,1
   B,0,switch,0
   F,0,RLED,0
   

   The rules for this text file are:

   • # at the beginning of a line indicates a comment
   • Each line specified how one bit of a signal is mapped to one board element
   • Each line is comma-separated with the following values
     • signal name: This must match the name of one of the signals in the top-level vhd file (testbench.vhd, for this lab).
     • signal bit: This is the index of the bit we are mapping. If the signal is only one bit (as in this lab), then just write "0". If the signal more than one bits, e.g. it is defined like this

                signal num : unsigned(3 downto 0);
               

       then specifying bit 0 means signal(0), i.e. the rightmost bit of the signal. You can specify bit 0, 1, 2, or 3 for the signal named num.
     • board element name: This is one of
       1. switch: for the switches
       2. hex: for the 7-segment displays
       3. gled: for the green LEDs
       4. rled: for the red LEDs
       5. key: for the key buttons
     • board element index: specifies which element, e.g. if it is 0 and the board element name is hex, then it is the rightmost 7-segment display. Board elements are numbers right to left, just like bits are.
     • segment index: specifies which of the 7 segments in the 7-segment display. This is relevant, only if the board element name is hex.
   • Download the Python code vcd_parser.py and vcd_movie.py and place them into your CS232 directory. This code is brand new and will certainly have bugs in it. Please let me know when you run into problems with it and I will do my best to fix them ASAP. I will put the most recent version on the web, so you can download it. So that you don't have copies of it proliferating, I think it is a good idea to put it in a top-level directory and replace it with updates.
   • Change to the directory with the Python code, and run vcd_movie.py with the vcd and mapping files. For me, the command is

     python vcd_movie.py lab01/testbench.vcd lab01/testbench_mapping.txt
     

     There are three control buttons

     • Start: begin the animation
     • Pause: pause the animation
     • Reset: Reset the time back to the beginning. As of the beginning of the semester, this doesn't work well unless you press the Pause button first.
     and a slider. The slider controls the amount of time between each timestep. It is only approximate. When the simulation is running, the current time step is indicated by the red bar on the time-line.

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(Alternate Simulation Method) Model a Circuit Using ModelSim

If you are using the Web Edition of Quartus on your own laptop, you may be able to use Modelsim to simulate your circuit.

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When you have completed the lab assignment, go ahead and get started on the first project.

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