-- CS232 Lab 6: stacker.vhd
-- Your name here
-- Date of the day you create this file

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity stacker is
          -- stacker ports		  
end entity;

architecture rtl of stacker is

	-- RAM ports
		
	-- internal signals and registers
	
begin
	
	-- port map the RAM
	
	-- connect the internal signals to their output signals
	
	-- state machine 
	process (clk, reset) -- remember to update the parameters accordingly
	begin
	
	end process;

end rtl;