-- to compile and test, use ghdl
--
-- ghdl -a mygate.vhd
-- ghdl -a testmygate.vhd
-- ghdl -e testmygate
-- ghdl -r testmygate --vcd=testmygate.vcd
-- gtkwave testmygate.vcd
--
library ieee;
use ieee.std_logic_1164.all;

entity mygate is
  port( A, B: in std_logic;
        Q: out std_logic );
end mygate;

architecture dataflow of mygate is

begin  -- dataflow

  Q <= A and B;

end dataflow;