library ieee;
use ieee.std_logic_1164.all;

entity swap is
  port( reset, clk: in std_logic;
        Q: out std_logic );
end swap;

architecture test of swap is

  signal A : std_logic := '0';          -- register A
  signal B : std_logic := '1';          -- register B

begin  -- test

  -- purpose: swapping values on the rising edge
  -- type   : sequential
  -- inputs : clk
  -- outputs: A, B
  main: process (clk)
  begin  -- process main
    if reset = '1' then
      A <= '0';
      B <= '1';
    elsif clk = '1' and clk'event then
      A <= B;                           -- swap the values
      B <= A;                           -- works b/c swaps occurs simultaneously
    end if;
  end process main;

  Q <= A; -- runs simultaneously with the process
  
end test;