-- to compile and test, use ghdl
--
-- ghdl -a mygate.vhd
-- ghdl -a testmygate.vhd
-- ghdl -e testmygate
-- ghdl -r testmygate --vcd=testmygate.vcd
-- gtkwave testmygate.vcd
--
library ieee;
use ieee.std_logic_1164.all;

entity testmygate is
end testmygate;

architecture test of testmygate is
  signal A : std_logic := '0';            -- input A
  signal B : std_logic := '0';            -- input B
  signal Q : std_logic;

  component mygate
    port (
      A, B : in  std_logic;
      Q    : out std_logic);
  end component;
begin  -- test

  A <= '0', '1' after 50 ns, '0' after 100 ns,
     '1' after 150 ns, '0' after 200 ns;
  B <= '0', '1' after 100 ns, '0' after 200 ns;
  
  A0 : mygate port map (
    A => A,
    B => B,
    Q => Q);


end test;