library ieee;
use ieee.std_logic_1164.all;

entity testswap is
end testswap;

architecture test of testswap is

  component swap
  port( reset, clk: in std_logic;
        Q: out std_logic );
  end component;

  signal clk : std_logic := '0';        -- clockdivider
  signal reset : std_logic := '0';      -- reset
  signal Q : std_logic;
  signal R : std_logic;
begin  -- test

  clk <= '0', '1' after 50 ns, '0' after 100 ns, '1' after 150 ns, '0' after 200 ns,
       '1' after 250 ns, '0' after 300 ns;
  reset <= '1', '0' after 10 ns;
  
  S: swap port map ( reset, clk, Q );   -- these circuits are executing in parallel
  T: swap port map ( reset, Q, R );

end test;