Fall 2019 RISC CPU Design
The register layout is shown in the graphic above. The instruction set is given below. It is modeled on the PowerPC RISC architecture, although the size and number of working registers is significantly reduced. Watch the video describing the components (registers, RAM, ROM, and ALU) and data flow. (Note: I make a mistake when I say that the CR output of the ALU should be port mapped to the Condition Register - it should actually be port-mapped to another register, and the assignment from that mapped register to the CR should happen after ALU operations (instructions later).)
Registers A-E, the Stack Pointer, the MBR, and the Instruction Register are all 16 bit registers. The MAR needs to have enough bits to address all of memory (8 bits). The input port is 8 bits, and the output port is 16 bits. The program counter is 8 bits, and the Condition Register is 4 bits. The ALU circuit takes in two 16-bit values and an opcode and outputs the 16-bit result as well as the 4-bits for the Condition Register (though note there is a separate signal mapped to the ALU's output and we assign to the CR only in particular states, so it is a little more complicated than I indicated in the video).
The instructions are 16 bits. All instructions have a 4-bit opcode in bits (15 downto 12), with some instructions having an additional one or two bits of opcode. The remaining bits are used to specify source and destination registers, addresses, or immediate values. Instructions that have an address make use of the low 8 bits of the instruction to hold the information.
| Instruction | opcode | Remaining bits |
|---|---|---|
| Load from RAM | 0000 | R-DDD-AAAAAAAA: DDD = dest (table B), R = add register E to immediate value if 1, AAAAAAAA - immediate address value |
| Store to RAM | 0001 | R-SSS-AAAAAAAA: SSS = src (table B), R = add register E to immediate value if 1, AAAAAAAA - immediate address value |
| Unconditional Branch | 0010 | UUUU-AAAAAAAA: U = unused, AAAAAAAA = immediate address value. |
| Conditional Branch | 0011 | 00-CC-AAAAAAAA: CC = condition (00 = zero, 01 = overflow, 10 = negative, 11 = carry), AAAAAAAA = immediate address value. |
| Call | 0011 | 01-UU-AAAAAAAA: the cpu should push the PC and CR on the stack and then jump to the immediate address value AAAAAAAA, U = unused. |
| Return | 0011 | 10-UU-UUUUUUUU: the cpu should pop the CR and then pop the PC to continue execution at the stored address. U = unused. |
| Exit | 0011 | 11-UU-UUUUUUUU: The CPU should enter a halt state and not leave until the user resets the circuit. U = unused |
| Push | 0100 | SSS-UUUUUUUUU: SSS = src (table C) U = unused, operation puts the value into memory at location SP and increments SP. |
| Pop | 0101 | SSS-UUUUUUUUU: SSS = dest (table C) U = unused, operation reads the value from memory at location SP-1 and decrements SP. |
| Store to Output | 0110 | SSS-UUUUUUUUU: SSS = source (table D) U = unused. |
| Load from Input | 0111 | DDD-UUUUUUUUU: DDD = dest (table B) U = unused. |
| Add | 1000 | SSS-TTT-UUU-DDD: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E), U = unused. |
| Subtract | 1001 | SSS-TTT-UUU-DDD: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E), U = unused. |
| And | 1010 | SSS-TTT-UUU-DDD: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E), U = unused. |
| Or | 1011 | SSS-TTT-UUU-DDD: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E), U = unused |
| Exclusive-or | 1100 | SSS-TTT-UUU-DDD: SSS = srcA (table E), DDD = dest (table B), TTT = srcB (table E), U = unused. |
| Shift | 1101 | R-SSS-UUUUU-DDD: SSS = srcA (table E), DDD = dest (table B), R = direction bit '0' = left, '1' = right, maintains sign bit, U = unused. |
| Rotate | 1110 | R-SSS-UUUUU-DDD: SSS = srcA (table E), DDD = dest (table B), R = direction bit '0' = left, '1' = right, U = unused. |
| Move | 1111 | T-(IIIIIIII or SSS-UUUUU)-DDD: DDD = dest (table B), T = if '1', treat next 8 bits as a sign-extended immediate value, else SSS = source location (table D), U = unused. |
Below are the tables that show how to interpret the various register selection fields.
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The ALU circuit takes in two source registers and an opcode, and it returns a destination value and a set of condition flags. The ALU opcodes correspond to the low three bits of the 4-bit opcode for instructions 1000 through 1111 (notice this includes the move operation which should just pass through the ALU, so the 111 operation should just assign SRCA to DEST). Assign the ALU opcode signal the IR bits 14 downto 12 in the Exeute-Setup state.
The condition register should be set by the ALU only for instructions at or above 1000: arithmetic, logical, and move instructions. This means we cannot directly port map the CR to the output of the ALU (we need an additional signal).
CPU States
The CPU defined above requires nine states: Start, Fetch, Execute-Setup, Execute-ALU, Execute-MemoryWait, Execute-Write, Execute-ReturnPause1, Execute-ReturnPause2, and Halt.
The Fetch state is a single clock cycle. The execute cycle can take anywhere from three to six clock cycles, depending on the instruction. The Execute-Setup, Execute-ALU, and Execute-Write, are necessary for all instructions. The Execute-MemoryWait state is optional for all instructions except LOAD, POP, and RETURN. The RETURN instruction requires the Execute-ReturnPause1 and Execute-ReturnPause2 after the Execute-Write state in order to load the instruction at the return address into the IR.
Below is a description of what needs to happen in each state. I also made a table describing what needs to happen in each state (columns) for each operation (row). There is also a short movie in which I describe the state machine.
- Start: The computer should go to this state upon reset and wait for at least three clock cycles for the memory to complete its startup. Then it should move to the Fetch state.
- Fetch: The circuit should grab the current instruction from the ROM, increment the PC, and move to the Execute-Setup state.
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Execute-Setup: The purpose of the setup phase is to take one of three actions.
- If the instruction is a load, store, push, pop, call, or return then set up the MBR and MAR and take whatever action is necessary with the stack pointer.
- If the instruction is an ALU operation or a move, then assign srcA and srcB according to the instruction.
- If the instruction is a branch, then assign the PC.
- If the instruction is an exit instruction, then the next state should be a halt state, otherwise the next state should be Execute-ALU.
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Execute-ALU: The purpose of this state is to let the ALU circuit process the inputs.
- If the instruction requires a write to the RAM, then the write enable line should be set high.
- If the instruction is reading from or writing to memory (PUSH, STORE, CALL, LOAD, POP, or RETURN), then go to the ExectureMemoryWait state. Otherwise, go to the Execute-Write state.
- Execute-MemWait: The instructions that are reading from or writing to memory, PUSH, STORE, CALL, LOAD, POP, RETURN, need an extra state for the memory data to become available (for the read) or properly stored (for the write). The next state is Execute-Write.
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Execute-Write: The purpose of the write phase is to take the information from the dest bus, the input port, or the memory buffer register and and write it to the correct location.
- If the instruction writes to the output port, that should occur here.
- The call and return functions will need to complete their actions.
- RETURN will write the return address to the PC and then move to the Pause-1 state.
- All instructions other than return can go back to the Fetch state.
- Execute-ReturnPause1: Used only for the RETURN instruction, this waits for the return address to propogate through the ROM. Move to the Execute-ReturnPause2 state.
- Execute-ReturnPause2: Used only for the RETURN instruction, this waits for the return address to propagate through the ROM. Move to the Fetch state.